The present invention relates, in general, to contacts for semiconductor integrated circuits and, more particularly, to via contact structures for semiconductor devices having multilayer metallization.
As semiconductor device dimensions approach the submicron level, one of the limiting factors for further reduction in size is area required for device interconnections. One possible solution is multilevel metallization in which two or more interconnect layers are formed on top of a device, separated by an interlayer dielectric, and coupled by holes, or vias, which are filled with a via metallization. Even with multilayer metallization, though, the area required for vias limits further reduction in device size. Photolithography technology has advanced so that submicron via windows can be formed reliably, but due to contact resistance and metal step coverage issues, it has not been possible to take advantage of these advances.
A major contributor to the resistance of the via metallization is contact resistance at a bottom and a top interface area, also known as contact areas, between the via metallization and the interconnect layers. This interfacial contact resistance is inversely proportional to the cross sectional area of the contact. Effective via metallization must have sufficient contact area at both the bottom and top of the via to provide a low resistance contact. Due to alignment tolerances when a via pattern is aligned to an underlying interconnect pattern, the via pattern must be made smaller than the underlying metal interconnect pattern. In the past, vias were etched into the interlayer dielectric so that the bottom contact area was the same as, or smaller than, the top contact area. Since the contact resistance is inversely proportional to the interfacial area of the contact, the small area of the via pattern, and particularly the small bottom contact area, led to higher contact resistance.
Another contributor to contact resistance is contamination of the interface between the via metallization and the interconnect layer. Any impurities, such as oxides, organic compounds, or the like, which alter the surface of the underlying interconnect layer from its as-deposited condition, will increase contact resistance. In the past, a top surface of the underlying interconnect layer was contaminated by the process of etching the via, and it was difficult to clean the top surface so as to return the surface to its as-deposited condition. It is thus advantageous to protect the underlying interconnect layer during the via etch process.
Small vias also resulted in current crowding at the bottom contact area which caused localized heating, increased resistance and made the contact less reliable due to electromigration effects. Current crowding was known to occur at metal corners which formed at the interface between the interconnect layer and the via metallization, resulting in higher current density at the corners than in the body of the via metallization. Current crowding effects significantly reduced the lifetime and reliability of the via metallization. It is important to note that due to the localized nature of the current crowding effect, it was not the cross sectional area of the via metallization that effected reliability, but instead the interface areas at the top and bottom of the via.
Another problem with previous multilayer metallization processes was filling the via with the via metallization without creating voids so that a high quality electrical contact was formed. Conventional metal deposition methods such as evaporation, sputtering, and reactive ion sputtering have been used to fill vias. These metal deposition processes are generically called physical deposition processes. Physical deposition processes form a layer on all exposed surfaces except surfaces that are blocked by physical topography barriers such as corners. These metal deposition methods thus resulted in poor step coverage within the via, which was aggravated as the aspect ratio, that is the ratio of height to width of the via, increased. Poor step coverage forced manufacturers to slope the via walls, which improved step coverage and decreased the aspect ratio, but also increased the dimensions of the contact.
Chemical deposition techniques, and chemical vapor deposition (CVD) techniques in particular, have also been used to form metal layers on semiconductors. Chemically deposited layers are known to deposit conformably around corners and into spaces that physical deposition processes cannot fill. Recently, CVD techniques which form a selective metal layer have been used to form via metallization. The CVD process can selectively deposit a metal, such as tungsten, onto conductive surfaces, while not depositing on dielectric surfaces such as oxide or nitride. Because they conformably coat the conductive surfaces, selective CVD processes can provide contacts and vias with superior fill quality.
A limitation of the selective CVD process was that by-products of the CVD reaction could damage the underlying interconnect metallization. In particular, a fluorine by-product of CVD tungsten deposition will react with aluminum interconnect metal, forming a high resistance layer between the interconnect and via metallizations. Therefore, it is desirable to protect the interconnect metallization during the CVD process.
Usually, a dry etch process such as plasma etching or reactive ion etching is used to etch the interlayer dielectric. The dry etch process causes a polymer film to form on the sidewalls of the via. The polymer film flaked off during subsequent processing, creating defects in the device and lowering yield. As the interlayer dielectric is cleared from the interconnect metal, some of the interconnect metal backsputtered onto the sidewalls of the via and incorporated into the polymer film. In the past it was difficult to remove this polymer film without damaging the exposed interconnect metal. Since selective CVD metal deposited on conductive materials, this backsputtered metal acted as a nucleation surface for the CVD metal formation, causing undesirable sidewall metal deposition. Sidewall metal deposition resulted in voids in the via metallization, and lower reliability of the via contact.
Accordingly, it is an object of the present invention to provide a method for producing a contact structure with increased contact area at the base of the via.
It is another object of the present invention to provide a method for producing a contact structure with improved reliability.
It is another object of the present invention to provide a via structure with reduced via resistance.
It is a further object of the present invention to provide a method for producing a contact structure which does not degrade underlying interconnect metal layers.
It is a further object of the present invention to provide a contact structure which can be easily down sized.
It is a still further object of the present invention to provide a method for producing a contact structure with improved alignment tolerance.